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| For Audio Equipment MN662724RPE Signal Processing LSI for CD Players Overview The MN662724RPE is a CD signal processing LSI that, on a single chip, combines an optics servo for the CD player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction), and digital servo processing for the spindle motor. (Other) Built-in playback pitch control function (normal speed only)(13%) Built-in support for jitter-free disc rotation synchronization playback Oscillator shutdown mode Power management mode Operating voltage 4.5 to 5.5V Features (Optics servo) Focus, tracking, and traverse servos Automatic adjustment functions for FO/TR gain, FO/TR offset, and FO/TR balance Built-in D/A converter for drive voltage output Built-in dropout countermeasures Anti-shock functions Built-in track cross counter (Digital signal processing) Built-in DSL and PLL Frame synchronization detection, holding, and insertion Subcode data processing Q data CRC check Built-in Q data register CIRC error detection and correction C1 decoder: duplex error correction C2 decoder: triplex error correction Built-in 16-K bits of RAM for de-interleaving Audio data interpolation Average, hold of previous values Soft muting Digital attenuation (256 levels) Software attenuation (256 levels) Auto cue detection function Digital audio interface (EIAJ format) Two audio data serial interfaces: One switchable between bit rates of 64 fs and 48 fs; the other fixed at 48 f s. (Spindle motor servo) CLV digital servo Switchable servo gain Applications CD Players MN662724RPE Pin Assignment For Audio Equipment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BYTCK/TRVSTOP CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH FLAG6/RESY SDAT48 TEST AVDD1 LRCK48 AVSS1 BCLK48 RSEL CSEL PSEL MSEL SSEL 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD X2 X1 VSS SBCK SUBC TOFS PCK/DSLB EFM/CK384 AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL PLAY PLLF2 LDON BDO RFDET TRCRS OFT VDET RFENV TE FE TBAL FBAL VREF FOD TRD KICK ECS ECM PC TVD TRV BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK (TOP VIEW) QFS080-P-1414 For Audio Equipment Block Diagram MN662724RPE CLVS CRC BLKCK CLDCK SBCK SUBC 66 67 13 62 56 55 DIGITAL AUDIO INTERFACE 74 AVSS1 72 AVDD1 65 FLAG 64 IPFLAG 68 DEMPH 69 FLAG6/RESY 80 SSEL 14 SQCK 15 SUBQ 51 AVSS2 50 AVDD2 53 PCK/DSLB 52 EFM/CK384 48 PLLF 41 PLLF2 47 DSLF 45 IREF 46 DRF 44 ARF 76 RSEL PSEL 78 16K SRAM 6 SUBCODE BUFFER TX EFM DEMODULATION SYNC INTERPOLATION SUBCODE DEMODULATION CLV SERVO 24 23 2 73 3 70 1 75 16 CIRC ERROR CORRECTION DEINTERLEAVE ECM PC LRCK LRCK48 SRDATA SDAT48 BCLK BCLK48 DMUTE VCO INTERPOLATION SOFT MUTING DIGITAL ATTENUATION PEAK DETECT AUTO CUE DSL*PLL 9 MLD 7 MCLK 8 MDATA TIMING GENERATOR VCO PITCH CONTROL VCOF SMCK FCLK PMCK CSEL MSEL X2 X1 STAT D/A CONVERTER 49 19 63 20 77 79 59 58 17 SERVO TIMING GENERATOR 38 36 MICROCOMPUTER INTERFACE 21 TRV 26 KICK 29 VREF 61 25 22 27 28 31 30 12 11 42 40 54 BYTCK/TRVSTOP ECS TVD TRD FOD TBAL FBAL TLOCK FLOCK PLAY LDON TOFS SERVO CPU OUTPUT PORT 43 WVEL 10 SENSE A/D CONVERTER INPUT PORT 37 35 VDET 39 60 57 4 5 18 71 32 FE 33 TE 34 RFENV TRCRS RFDET VDD VSS DVDD1 DVSS1 RST TEST BDO OFT MN662724RPE Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Symbol BCLK LRCK SRDATA DV DD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT I/O O O O I I O I I I O O O O I O I O For Audio Equipment Function Description SRDATA bit clock output. Left/right channel discrimination signal output. Serial data output. Power supply for digital circuits. Ground for digital circuits. Digital audio interface output signal. Microcomputer command clock input. (Data is latched at rising edge.) Microcomputer command data input. Microcomputer command load signal input. Focus servo pull-in signal. Tracking servo pull-in signal. "L" level: load. Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND) "L" level: pull-in state. "L" level: pull-in state. Subcode block clock signal (fBLKCK=75Hz) External clock input for subcode Q register Subcode Q data output Muting input. (Effective only for an output bit rate of 64 fs) "H" level: muting. Status signal. (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK, FLAG6, SENSE, FLOCK, and TLOCK) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 RST SMCK PMCK TRV TVD PC ECM ECS KICK TRD FOD VREF FBAL TBAL FE TE RFENV VDET OFT TRCRS I O O O O O O O O O O I O O I I I I I I Reset input. "L" level: reset. If MSEL is "H" level, 8.4672 MHz clock signal is outputted. If MSEL is "L" level, 4.2336 MHz clock signal is outputted. 88.2kHz clock signal output. Traverse forced feed output. Traverse drive output. Spindle motor ON signal. "L" level: ON (default). Spindle motor drive signal (forced mode output). (tristate) Spindle motor drive signal (servo error signal output) Kick pulse output. Tracking drive output. Focus drive output. Reference voltage for D/A output (TVD, ECS, TRD, FOD, FBAL, TBAL, and TOFS). Focus balance adjustment output. Tracking balance adjustment output. Focus error signal input. Tracking error signal input. RF envelope signal input. Offtrack signal input. Track cross signal input. (analog input) (analog input) (analog input) "H" level: offtrack. (analog input) (tristate) (tristate) Vibration detection signal input. "H" level: vibration detected. For Audio Equipment Pins Descriptions (continued) Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Symbol RFDET BDO LDON PLLF2 PLAY WVEL ARF IREF DRF DSLF PLLF VCOF AV DD2 AV SS2 EFM or CK384 I/O I I O I/O O O I I I I/O I/O I/O I I O MN662724RPE Function Description RF detection signal input. "L" level: detected. Dropout signal input. "H" level: dropout Laser ON signal output. "H" level: ON. PLL loop-filter characteristic switching pin. Play signal output. Double-speed status signal output. RF signal input. Reference current input pin DSL bias pin. DSL loop-filter pin. PLL loop-filter pin. VCO loop-filter pin. Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D converter). Ground for analog circuits (DSL, PLL, D/A converter output, and A/D converter). EFM signal output. * EFM output. * Crystal oscillator 16.9344 MHz output. * 384 fs output from signal processing block. (During variable-pitch operation, this is the VCO clock.) Commands permit switching among the above three outputs. "H" level: play. "H" level: double-speed. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PCK or DSLB TOFS SUBC SBCK VSS X1 X2 VDD BYTCK or TRVSTOP CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH O O O I I I O I O O O O O O O O Clock for PLL or DSL balance output. Tracking offset adjustment output. Subcode serial output. Clock input for subcode serial output. Ground for oscillator circuit. Crystal oscillator circuit input pin. Crystal oscillator circuit output pin. Oscillator circuit power supply. f PCK=4.3218MHz f=16.9344MHz, 33.8688MHz f=16.9344MHz, 33.8688MHz During default operation, byte clock signal output. During command execution, traverse stop signal output. "H" level: stop mode. Subcode frame clock signal output pin. Crystal frame clock signal output. Interpolation flag signal output. Flag signal output. Spindle servo phase synchronization signal output. "H" level: CLV. "L" level: rough servo. Subcode CRC check result output. De-emphasis detection signal output. "H" level: OK. "L" level: no good. "H" level: on. (f CLDCK=7.35kHz) (f FCLK=7.35kHz) "H" level: interpolation. MN662724RPE Pin Descriptions (continued) Pin No. 69 Symbol FLAG6 or RESY I/O O For Audio Equipment Function description During default operation, FLAG6 output, that is the resetting signal for the address of RAM used to de-interleave error correction data. "L" level: address reset. During command execution, RESY output, that is the frame resynchronization signal. "H" level: synchronized. "L" level: out of sync. Keep this at "H" level. 70 71 72 73 74 75 76 77 78 79 SDAT48 TEST AV DD1 LRCK48 AVSS1 BCLK48 RSEL CSEL PSEL MSEL O I I O I O I I I I Serial data output for bit rate 48 fs. Test pin. Power supply for digital circuits. Left/right channel discrimination signal output for bit rate 48 fs. Ground for digital circuits. Bit clock output for bit rate 48 f s. RF signal polarity selection pin. "H" level: bright level is "H." "L" level: bright level is "L." Crystal oscillator frequency specification pin. Test pin. SMCK pin output. "H" level: 33.8688 MHz. "L" level: 16.9344 MHz Keep this at "L" level. SMCK frequency selection pin. "H" level: 8.4672 MHz. "L" level: 4.2336 MHz. 80 SSEL I SUBQ pin output mode selection pin. "H" level: Buffered Q code mode. "L" level: CLDCK synchronization mode. For Audio Equipment Package Dimensions (Unit: mm) QFS080-P-1414 MN662724RPE 16.20.2 14.00.2 60 61 41 40 0.825 14.00.2 80 21 1 0.65 20 16.20.2 1.10.1 2.00.2 0.3 -0.05 2.10.3 +0.10 0.15 SEATING PLANE 0.10.1 0.15 0.550.1 0 to 10 +0.10 -0.05 |
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